The present invention relates to a clock recovery circuit for use in digital communications.
Among the various modulation systems employed in digital communications, a typical example is .pi./4-shift quaternary phase-shift keying (QPSK), which encodes two-bit data values as shifts of -3.pi./4, -.pi./4, .pi./4, and 3.pi./4 radians in the phase of a carrier signal, shifting the phase by a multiple of .pi./4 in each symbol interval. This system has certain advantages for mobile communication systems, including high transmission efficiency and a compact, low-power differential demodulator configuration.
FIG. 10 shows the demodulator configuration. The modulated carrier signal is received at an input terminal 1. A local oscillator 2 generates an unmodulated carrier signal with a frequency substantially equal to the frequency of the modulated carrier signal. An instantaneous phase detection circuit 3 compares the phase of the modulated carrier with the phase of the unmodulated carrier and converts the difference between them to a digital value, which it outputs as an instantaneous phase signal 4. A differential phase computing circuit 5 takes the difference between the instantaneous phase signal 4 and the instantaneous phase signal 4 delayed by one symbol interval, to obtain a differential phase signal 6.
The differential phase signal 6 is supplied to a clock recovery circuit 7 and data recovery circuit 8. The clock recovery circuit 7 recovers a clock signal, which it outputs at an output terminal 9 and also sends to the data recovery circuit 8. The data recovery circuit 8 samples the differential phase signal 6 at timings given by the clock signal, decodes the sampled values to recover bits of data, and outputs the data at an output terminal 10. The clock signal output at terminal 9 is used in subsequent processing of the data output at terminal 10.
FIG. 11 shows an eye pattern obtained by superimposing, on an oscilloscope screen for example, all of the trajectories that can be followed by the differential phase signal 6. In FIG. 11 the horizontal sweep time is set to three symbol intervals, corresponding to six bits of data.
The clock recovery circuit 7 has a magnitude comparator that compares the differential phase signal 6 with a preset level and generates a timing pulse when the differential phase signal 6 crosses this level. This is illustrated in FIG. 11, which shows timing pulses 12 generated when a particular trajectory 14 crosses a level (denoted level one) corresponding to a phase angle of zero radians.
The timing pulses 12 from the magnitude comparator are conventionally supplied directly to a digital phase-locked loop. The digital phase-locked loop generates a clock signal 16 synchronized so that, for example, falling transitions of the clock signal 16 coincide, on the average, with the timing pulses 12. This clock signal 16 is the clock signal output by the clock recovery circuit 7 at output terminal 9 in FIG. 10.
The digital phase-locked loop operates by dividing the frequency of a signal supplied from an oscillator by an integer N to obtain an internal clock signal, which is then further divided by a fixed amount to obtain the recovered clock signal 16. If a falling transition of the clock signal 16 leads the timing pulses 12, the oscillator frequency is divided by a larger integer N+L for a certain number J of internal clock cycles, to retard the phase of the clock signal 16. After J internal clock cycles, the division ratio reverts to N. If a falling transition of the clock signal 16 lags the timing pulses 12, the oscillator frequency is divided by N-L for J internal clock cycles, to advance the clock phase.
The data recovery circuit 8 samples the differential phase signal 6 at rising transitions of the clock signal 16, thereby acquiring samples at points such as Tn in FIG. 11 at which the eye pattern is most open. These are the optimum timings for obtaining unambiguous values from which to recover data.
Trajectory 14 in FIG. 11 is one of two possible trajectories that can be followed during a so-called preamble period employed in many digital communication systems, in which the transmitter repeatedly sends the synchronization pattern "1001" and the differential phase signal 6 alternates between phase angles of 3.pi./4 and -.pi./4. The other trajectory 20 that can be followed in the preamble is identical to trajectory 14, but shifted by one symbol interval. The synchronization pattern is transmitted for the express purpose of enabling the phase-locked loop in the demodulator to synchronize with the phase of the differential phase signal 6.
After the preamble, the transmitter transmits a data header, then message data, during which the differential phase signal 6 can follow any of the sixteen trajectories shown in FIG. 11. Four of these trajectories cross level one at exactly the right timings 18 and 19 for locking the phase of the clock signal 16, and four more trajectories cross level one at points fairly near these timings 18 and 19. Because the other eight trajectories do not cross level one at all, the phase-locked loop only receives timing pulses about half the time during transmission of the message data, which is still adequate for keeping the clock signal correctly synchronized.
The trajectories 14 and 20 that occur in the preamble are among the four that do not cross level one at the right timings 18 and 19 and instead "jitter" around these timings by an amount denoted .+-..delta. in FIG. 11. When the clock signal 16 is locked in correct phase, this jitter does not cause loss of phase lock. Falling transitions of the clock signal 16 alternately lead and lag the timing pulses 12 by .delta., causing the phase-locked loop alternately to retard and advance the clock signal 16, with zero net effect on the clock phase.
If the clock signal is 180.degree. out of phase, as shown by waveform 22 in FIG. 11, its falling transitions again lead and lag the timing pulses 12 alternately, causing again the phase-locked loop alternately to retard and advance the clock phase, with zero net effect. Unfortunately, the clock signal then becomes deadlocked in an out-of-phase state. Although this deadlock condition does not arise frequently, it occurs often enough to pose a communication reliability problem.
One solution to the deadlock problem, previously proposed by the inventor, is to adjust the phase of the clock signal by an amount equal to twice the jitter value .delta. when the clock signal leads or lags the timing pulses 12 by more than a certain angle. In practice, however, the jitter .delta. can attain values close to 40.degree., requiring a phase adjustment of approximately 80.degree.. (In FIG. 11 the jitter is 60.degree., requiring an adjustment of 120.degree..) A system configured to perform adjustments of this size would be highly sensitive to noise, and could easily lose phase lock if the adjustment were to be applied by mistake.
Another possible solution is to detect crossings of level two instead of level one in FIG. 11, which corresponds to detecting a phase angle of .pi./4 instead of zero. Pulses will then be output at the correct timings 18 and 19 during the preamble, and without jitter.
After the preamble ends, however, level two becomes inappropriate, because it is crossed by only four of the sixteen trajectories in the eye pattern, and is crossed at the correct timings 18 and 19 by only the two trajectories 14 and 20. After the preamble ends, it would be preferable to switch crossing detection from level two back to level one, which provides twice as many correctly-timed pulses for controlling the phase-locked loop.
Switching between levels one and two, however, requires a determination as to whether or not the signal currently being received belongs to the preamble. Distinguishing between a preamble signal and a message data signal is a complex task, requiring the assistance of an intelligent circuit such as a microprocessor. Providing a microprocessor in the clock recovery circuit, to be used for this purpose alone, would be impractically expensive. Using an external microprocessor is also an unattractive solution, because an external processor would be loaded with other data-processing and control functions, and hence would not be readily able to undertake the task of determining the data type for the clock recovery circuit.